WEEK 1
INTERNSHIP UNDER DR GS JAVED SIR
INTERN NAME - AFZAL MAL IK
COLLEGE/U NIVE RSITY ZAKIR H U SAIN COLL EGE OF E N G G. & TEC H .
ALIGARH MUSL I M UNIVERSIT Y
COURSE- BAC H E LOR OF TECHNOLOGY (E L EC TRONICS ENGG.)
YEA R SECO ND
WEEK 1 INTERNSHIP PLAN
To be able to perform .dc /.op / .tran Simulations
To design Common Source and Common Drain Amplifier ( Used Gm
over Id Method )
SOFTWARE USED : LT Spice , MS Excel
BASIC CIRCUIT SIMULATIONS
.DC , .OP AND .TRAN SIMULATION OF
BASIC CIRCUITS USING LT SPICE
DESIGN OF COMMON SOURCE
AMPLIFIER ( USING GM OVER
ID METHOD )
PARAMETER CHARTS
IN ORDER TO DESIGN AN AMPLIFIER USING GM OVER ID
METHODOLOGY WE REQUIRE PARAMETER CHARTS :
a) Primary Charts
1) Gm/Gds vs Gm/Id
2) Id/W vs Gm/Id
3) Ft vs Gm/Id
b) Secondary Charts
1)Cgd/Cgg vs Gm/Id
2)Cdd/Cgg vs Gm/Id
Plotting Parameter Charts
USING LT SPICE AND MS EXCEL
MODEL FILE : 180n
LT SPICE SETUP TO PLOT CHARTS FOR NMOS
AFTER MAKING THE SETUP IN LT SPICE
Id vs Vgs is plotted by sweeping vgs from 0 to 1.8 V
Gm [ d(Id(M1)] vs Vgs is plotted by sweeping vgs from 0 to 1.8 V
Id vs Vds is plotted by sweeping vds from 0 to 1.8 V
Gds [ d(Id(M1)] vs Vds is plotted by sweeping vgs from 0 to 1.8 V
All this data is transferred in MS Excel and then
Gm/Gds vs Gm/Id is plotted
Id/W vs Gm/Id is plotted
Hence , we got two of the parameter charts that are required to
design Common Source Amplifier
0
50
100
150
200
250
0 5 10 15 20 25 30 35
gm/gds
gm/id
PLOT OF Gm/Gds vs Gm/Id
180n
360n
540n
720n
900n
0
10
20
30
40
50
60
70
80
90
0 5 10 15 20 25 30 35
Id/W
gm/Id
PLOT OF Id/W vs Gm/Id
180n
360n
540n
720n
900n
LT SPICE SETUP TO PLOT CHARTS FOR PMOS
0
100
200
300
400
500
600
0 5 10 15 20 25 30
gm/gds
gm/Id
Gm/Gds vs Gm/Id
180n
360n
540n
720n
900n
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30
Id/W
Gm/Id
PLOT OF Id/W vs Gm/Id
180n
360n
540n
720n
900n
COMMON SOURCE AMPLIFIER
USING NMOS AND PASSIVE LOAD
MODEL FILE : 180n
SPECIFICATIONS
GBW=800MHz , VDD=1.8V , L=0.36u
CALCULATIONS
GBW=800MHz , L=0.36u , Vdd=1.8V, Model file = 180n
Let GAIN (A) = 10
f(-3db) =

G = 80MHz let CL=5pF
USING f(-3db) =
CLRout = 397.88 ohm
Now , Gain (A) = Gm Rout Gm=25.1 mS
Now , Let Gm/Id = 10.2 Id = 2.46 mA
(From NMOS Parameter Charts)
Gm/Gds = 69.9 Gds=359 uS
AS Ro=1/Gds , Ro=2785 ohm
(From NMOS Parameter Charts)
Id/W= 13.6 W=180u
CALCULATIONS
Now Rout = Ro || RLRL = RoRout
(Ro Rout)
RL = 464.197 ohms
Now, Vgs is calculated from Gm/Id vs Vgs Curve in LT Spice
For , Gm/Id = 10.2
Vgs = 702mV = 0.702V
SCHEMATIC IN LT SPICE
.OP ANALYSIS IN LT SPICE
TRANSIENT ANALYSIS IN LT SPICE
FREQUENCY RESPONSE IN LT SPICE
SIMULATIONS RESULT
GBW=837MHz
Gain= 10.2737
COMMON SOURCE AMPLIFIER
USING PMOS AND PASSIVE LOAD
MODEL FILE : 180n
SPECIFICATIONS
GBW=800MHz , VDD=1.8V , L=0.36u
CALCULATIONS
GBW=800MHz , L=0.36u , Vs=1.8V, Model file = 180n
Let GAIN (A) = 10
f(-3db) =

G= 80MHz let CL=5pF
USING f(-3db) =
CLRout = 397.88 ohm
Now , GAIN (A) = Gm Rout Gm=25.1 mS
Now , Let Gm/Id = 10.2 Id = 2.46 mA
(From NMOS Parameter Charts)
Gm/Gds = 72.2 Gds=347.64 uS
AS Ro=1/Gds , Ro=2876.5 ohm
(From NMOS Parameter Charts)
Id/W= 3.3 W=745u
CALCULATIONS
Now Rout = Ro || RLRL = RoRout
(Ro Rout)
RL = 461.75 ohms
Now, Vgs is calculated from Gm/Id vs Vgs Curve in LT Spice
For , Gm/Id = 10.2
Vg = 1.1V
SCHEMATIC IN LT SPICE
TRANSIENT ANALYSIS IN LT SPICE
FREQUENCY RESPONSE IN LT SPICE
SIMULATIONS RESULT
GBW=763MHz
Gain= 10.756
COMMON DRAIN AMPLIFIER
(SOURCE FOLLOWER)
USING NMOS AND RESITANCE
MODEL FILE : 180n
SPECIFICATIONS
VDD=1.8V , L=0.36u , GAIN(A)=0.95
Rout=50 ohm, CL= 5pf
CALCULATIONS
VDD=1.8V , L=0.36u , GAIN(A)=0.95
Rout=50 ohm, CL= 5pf
Using B.W =
2CLBW= 636.61MHz
Now , Gain (A) = 󰇛󰇜
󰇛  and Rout = 1/Gm||Ro||Rs
On solving both the equation , we get
Gm=19mS 󰇛󰇜=1000 ohm
Now , let Gm/Id = 15.1 Id=1.26mA
Gm/Gds = 38.2 Gds=497uS Ro=2.012 K ohm
And hence , Rs=1.988 K ohm ( by further inspection taken as 720 ohm )
Vgs = 0.543V Vg = vgs + vs =1.443 V
Id/W=5.65 W=223u
SCHEMATIC IN LT SPICE
TRANSIENT ANALYSIS IN LT SPICE
FREQUENCY RESPONSE IN LT SPICE
Feedback I got
Specifications are not exactly matching with simulations ,
W/L ratio is very high , so now I have to redesign them by
making slight modification in design approach
THANK YOU